In contemporary electronic circuits, such as, for example, input/output (IO) buffers, used in various applications, including but not limited to telecommunications, data networking, frequency synthesis, clock and data recovery (CDR), etc., it is often desirable to convey data at relatively high speeds (e.g., 300 megabits per second (Mb/s) or greater). Such high-speed data is often transmitted in a relatively noisy environment. Moreover, the trend to lower operating voltages and power consumption, particularly in mobile electronic devices, only worsens signal-to-noise ratios, thereby further encumbering reliable data transmission efforts.
In order to meet modern high-speed data interfacing specifications, complementary metal-oxide-semiconductor (CMOS) current-mode logic (CML) buffers were introduced (see, e.g., M. Mizuno et al., “A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic,” IEEE J. Solid-State Circuits, Vol. 31, No. 6, pp. 784-791, June 1996, the disclosure of which is incorporated by reference herein). CML, sometimes referred to as source-coupled logic (SCL), is based on a differential digital logic architecture and is intended to transmit data at high speeds (e.g., gigabits per second (Gb/s) or greater). FIG. 1 is a schematic diagram illustrating a conventional CML transmission architecture 100 including a source device 102, which may be a transmitter, and a destination device 104, which may be a receiver, coupled together via a differential transmission line 106. Transmission using CML is typically point-to-point, unidirectional, and is often terminated at the destination device 104 using 50-ohm resistors to the positive voltage supply, which may be VDD, on both differential lines 106 as shown.
A CML buffer circuit is generally required to provide an output voltage swing (e.g., Voh to Vol, or Vol to Voh) of about 400 millivolts (mV), for most CML specifications. However, in many applications, particularly those applications requiring a low voltage supply (e.g., 1.0 volt or less), it is challenging to achieve the required output voltage swing and yet still meet other prescribed specifications (e.g., power dissipation, output common-mode (CM), switching speed, etc.). Accordingly, standard CML buffer circuit architectures are impractical and/or undesirable.